Paper Abstract and Keywords |
Presentation |
2014-04-25 14:00
Construction of Design Environment for Asynchronous Circuits using DDL Cell Library Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging effect, which exhibit random characteristics even in the neighboring components, have been one of main issues. QDI-model-based dual-rail asynchronous circuits are promising implementation against these random variations. However, the dual-rail circuits which are composed by the normal single-rail standard-cell libraries may be twice larger than the corresponding single-rail circuits. In this paper, we propose DDL (Differential Domino Logic) cell libraries and their logic synthesis libraries in order to design high-performance and small-area asynchronous circuits. The cell libraries contain 12 DDL cells, which can implement any function by one of them. We also design three synthesis libraries in the Liberty format and compare them. We will show some evaluation results using the Nangate 45nm process technologies. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Asynchronous circuits / Dual-rail encoding / QDI model / DDL cell library / Logic synthesis / Technology mapping / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 21, CPSY2014-2, pp. 3-8, April 2014. |
Paper # |
CPSY2014-2 |
Date of Issue |
2014-04-18 (CPSY, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2014-2 DC2014-2 |
Conference Information |
Committee |
CPSY DC |
Conference Date |
2014-04-25 - 2014-04-25 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
CPSY |
Conference Code |
2014-04-CPSY-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Construction of Design Environment for Asynchronous Circuits using DDL Cell Library |
Sub Title (in English) |
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Keyword(1) |
Asynchronous circuits |
Keyword(2) |
Dual-rail encoding |
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QDI model |
Keyword(4) |
DDL cell library |
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Logic synthesis |
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Technology mapping |
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1st Author's Name |
Masashi Imai |
1st Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
2nd Author's Name |
Hiromasa Igarashi |
2nd Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
3rd Author's Name |
Sanshiro Kudo |
3rd Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-04-25 14:00:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
CPSY2014-2, DC2014-2 |
Volume (vol) |
vol.114 |
Number (no) |
no.21(CPSY), no.22(DC) |
Page |
pp.3-8 |
#Pages |
6 |
Date of Issue |
2014-04-18 (CPSY, DC) |
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