Paper Abstract and Keywords |
Presentation |
2014-04-18 10:30
[Invited Talk]
A 7ns-Access-Time 25μW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa (Toshiba), Kenji Hashimoto, Ichiro Wakiyama (TOSMEC), Shinji Miyano, Takehiko Hojo (Toshiba) ICD2014-12 Link to ES Tech. Rep. Archives: ICD2014-12 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Low leakage 128kb SRAM with 65 nm technology that consumes only 3.5nA (27fA/b) in the retention mode is fabricated. Operation power consumption is also reduced to 25μW/MHz by adopting quarter array activation scheme(QAAS) charge shared hierarchical bit line(CSHBL). Its leakage current is negligible small compared to the deep sleep mode current of the low power MCU, all of SRAMs in the chip can be awaken even in the deep sleep mode. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / Low Lekage Current / MCU / XLLSRAM / QAAS / CSHBL / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 13, ICD2014-12, pp. 59-64, April 2014. |
Paper # |
ICD2014-12 |
Date of Issue |
2014-04-10 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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Download PDF |
ICD2014-12 Link to ES Tech. Rep. Archives: ICD2014-12 |