Paper Abstract and Keywords |
Presentation |
2014-04-18 11:20
[Invited Lecture]
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit Keiichi Kushida, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Azuma Suzuki, Yusuke Niki, Miyako Shizuno, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2014-13 Link to ES Tech. Rep. Archives: ICD2014-13 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high temperature (HT) using a BL power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A test-chip is fabricated in a 28nm CMOS technology with a 0.120μm2 6T-SRAM cell. With these schemes, active and standby power consumptions at 25°C are reduced by 27% and 85%, respectively. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
A Dual-power supply SRAM / Power reduction / Digital LDO / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 13, ICD2014-13, pp. 65-70, April 2014. |
Paper # |
ICD2014-13 |
Date of Issue |
2014-04-10 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2014-13 Link to ES Tech. Rep. Archives: ICD2014-13 |
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