Paper Abstract and Keywords |
Presentation |
2014-03-16 09:00
The design and implementation of area-efficient processor "Raishodo" Akifumi Fujita, Naruki Kurata (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Masahiro Goshima, Shuichi Sakai (Univ. of Tokyo) CPSY2013-107 DC2013-94 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Although a superscalar processor has high perfomance, its circuit area is very large. Area reduction of a superscalar processor can reduce power consumption and can increase the number of cores on a die. This paper describes the design and implementation of a superscalar processor called "Raishodo", which achieves both small area and high performance. Raishodo adopts some methods to reduce the circuit area. Some of them are at the architecture-level those reduce the area of multi-port memories. The others are at the circuit-level those efficiently compose multi-port memories on an FPGA. The paper shows that Raishodo works on an FPGA and its resource consumption is very small. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Superscalar Processor / Out-of-Order Execution / Circuit Area / FPGA / Multi-port RAM / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 497, CPSY2013-107, pp. 229-234, March 2014. |
Paper # |
CPSY2013-107 |
Date of Issue |
2014-03-08 (CPSY, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2013-107 DC2013-94 |
Conference Information |
Committee |
CPSY IPSJ-EMB IPSJ-SLDM DC |
Conference Date |
2014-03-15 - 2014-03-16 |
Place (in Japanese) |
(See Japanese page) |
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Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
CPSY |
Conference Code |
2014-03-CPSY-EMB-SLDM-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
The design and implementation of area-efficient processor "Raishodo" |
Sub Title (in English) |
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Keyword(1) |
Superscalar Processor |
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Out-of-Order Execution |
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Circuit Area |
Keyword(4) |
FPGA |
Keyword(5) |
Multi-port RAM |
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1st Author's Name |
Akifumi Fujita |
1st Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Naruki Kurata |
2nd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Ryota Shioya |
3rd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
4th Author's Name |
Masahiro Goshima |
4th Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
5th Author's Name |
Shuichi Sakai |
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The University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2014-03-16 09:00:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
CPSY2013-107, DC2013-94 |
Volume (vol) |
vol.113 |
Number (no) |
no.497(CPSY), no.498(DC) |
Page |
pp.229-234 |
#Pages |
6 |
Date of Issue |
2014-03-08 (CPSY, DC) |
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