IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2014-03-05 13:50
Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB)
Tatsuki Saigusa, Kimiyoshi Usami (Shibaura Inst. of Tech) VLD2013-162
Abstract (in Japanese) (See Japanese page) 
(in English) Silicon on thin BOX(SOTB) is one of FD-SOI device.It is possible to operate with ultra-low voltage of 0.4V and greatly change the threshold voltage of a transistor by body biasing.So far, a design technique that realizes multi-vth using body biasing has been proposed.After designing the circuit which consists of only high threshold transistors, the threshold voltage is lowered only at the area which needs high-speed operation by applying body bias.In this research, we proposed a versatile design methodology and performed the evaluation for it.We show a comparison of a multi-Vth design and the design methodology that we proposed.
Keyword (in Japanese) (See Japanese page) 
(in English) Silicon-on-Thin-BOX / Body Bias / Multi Vth / Leakage Power / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 454, VLD2013-162, pp. 153-158, March 2014.
Paper # VLD2013-162 
Date of Issue 2014-02-24 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-162

Conference Information
Committee VLD  
Conference Date 2014-03-03 - 2014-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2014-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB) 
Sub Title (in English)  
Keyword(1) Silicon-on-Thin-BOX  
Keyword(2) Body Bias  
Keyword(3) Multi Vth  
Keyword(4) Leakage Power  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Tatsuki Saigusa  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech)
2nd Author's Name Kimiyoshi Usami  
2nd Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2014-03-05 13:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-162 
Volume (vol) vol.113 
Number (no) no.454 
Page pp.153-158 
#Pages
Date of Issue 2014-02-24 (VLD) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan