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| Presentation | 2014-03-05 15:45 A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design Tomoyuki Yokogawa, Daichi Higashiyama (Okayama Pref. Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Pref. Univ.)  VLD2013-166 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we show a case study where a design of 8bit microcomputer M8R, which is described by Verilog-HDL, is verified using symbolic model checker NuSMV.We provide a framework for translating a Verilog-HDL description into an SMV model.We also show approaches to simplify the Verilog-HDL description for model size reduction.We extract the decode procedure of M8R and represent the procedure as an input of SMV.We show the verification results using NuSMV. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | formal verification / Velilog-HDL / symbolic model checking / SMV / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 454, VLD2013-166, pp. 177-182, March 2014. | |
| Paper # | VLD2013-166 | |
| Date of Issue | 2014-02-24 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-166 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2014-03-03 - 2014-03-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design |
| Sub Title (in English) | |
| Keyword(1) | formal verification |
| Keyword(2) | Velilog-HDL |
| Keyword(3) | symbolic model checking |
| Keyword(4) | SMV |
| Keyword(5) | |
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| 1st Author's Name | Tomoyuki Yokogawa |
| 1st Author's Affiliation | Okayama Prefectural University (Okayama Pref. Univ.) |
| 2nd Author's Name | Daichi Higashiyama |
| 2nd Author's Affiliation | Okayama Prefectural University (Okayama Pref. Univ.) |
| 3rd Author's Name | Masafumi Kondo |
| 3rd Author's Affiliation | Kawasaki University of Medical Welware (Kawasaki Univ. of Medical Welfare) |
| 4th Author's Name | Yoichiro Sato |
| 4th Author's Affiliation | Okayama Prefectural University (Okayama Pref. Univ.) |
| 5th Author's Name | Kazutami Arimoto |
| 5th Author's Affiliation | Okayama Prefectural University (Okayama Pref. Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-03-05 15:45:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-166 |
| Volume (vol) | vol.113 |
| Number (no) | no.454 |
| Page | pp.177-182 |
| #Pages | 6 |
| Date of Issue | 2014-02-24 (VLD) |
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