Paper Abstract and Keywords |
Presentation |
2014-03-04 14:10
On-wafer de-embedding pattern design for reduced uncertainty under an area constraint Masafumi Suizu, Akihiko Orii, Kyoya Takano, Mizuki Motoyoshi, Kosuke Katayama, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima (Hiroshima Univ.) MW2013-203 Link to ES Tech. Rep. Archives: MW2013-203 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
To obtain the characteristics of the individual devices in the high-frequency measurement, de-embedding is required to remove the influence of the pads from the measurement results. For more accurate extraction of parameters, it is necessary to consider the uncertainty of the on-wafer de-embedding. We propose a method for designing the layout of on-wafer de-embedding patterns for multiline TRL with minimal uncertainty in de-embedding under a chip area constraint. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
On-wafer de-embedding / Uncertainty / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 460, MW2013-203, pp. 35-40, March 2014. |
Paper # |
MW2013-203 |
Date of Issue |
2014-02-25 (MW) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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MW2013-203 Link to ES Tech. Rep. Archives: MW2013-203 |