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| Presentation | 2014-03-03 16:25 Secure scan design using improved random order scans and its evaluations Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2013-141 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Scan test using scan chains is one of the most important DFT techniques. On the other hand, scan-based attacks are reported which can retrieve the secret key in crypto circuits by using scan chains. Secure scan architecture is strongly required to protect scan chains from scan-based attacks. In this paper, we propose an improved version of random order scans as a secure scan architecture. In our improved random order scans, a scan chain is partitioned into multiple sub-chains. The structure of the scan chain changes dynamically by selecting a subchain to scan out using enable signals. We also discuss testability and security of our improved random order scans and demonstrate their effectiveness through implementation results. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | design for testability / scan chain / secure scan architecture / security / testability / area-overhead / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 454, VLD2013-141, pp. 43-48, March 2014. | |
| Paper # | VLD2013-141 | |
| Date of Issue | 2014-02-24 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-141 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2014-03-03 - 2014-03-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Secure scan design using improved random order scans and its evaluations |
| Sub Title (in English) | |
| Keyword(1) | design for testability |
| Keyword(2) | scan chain |
| Keyword(3) | secure scan architecture |
| Keyword(4) | security |
| Keyword(5) | testability |
| Keyword(6) | area-overhead |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masaru Oya |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Yuta Atobe |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Youhua Shi |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Masao Yanagisawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Nozomu Togawa |
| 5th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-03-03 16:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-141 |
| Volume (vol) | vol.113 |
| Number (no) | no.454 |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2014-02-24 (VLD) |
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