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Paper Abstract and Keywords
Presentation 2014-01-29 10:25
Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76
Abstract (in Japanese) (See Japanese page) 
(in English) Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high energy efficiency, some of recent mobile devices are often required to execute performance centric jobs. In order to increase the clock frequency, introducing pipelined structure into each PE is a straight forward way, but the frequent pipeline stall will be caused by the data hazard between multiple PEs. In order to mitigate the influence of data hazard between PEs, a tiny vector instruction mechanism is introduced. With a single vector instruction, a small number of data are continuously processed in the pipeline of the PE. The pipeline stalls are removed without increasing the number of hardware contexts, thus the amount of configuration data. MuCCRA-4 with tiny vector instructions improves the performance by almost 4 times as the base DRPA(MuCCRA-3).
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processor / Pipeline structure / Vector instruction / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 418, RECONF2013-76, pp. 119-124, Jan. 2014.
Paper # RECONF2013-76 
Date of Issue 2014-01-21 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-122 CPSY2013-93 RECONF2013-76

Conference Information
Conference Date 2014-01-28 - 2014-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2014-01-SLDM-CPSY-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array 
Sub Title (in English)  
Keyword(1) Dynamically Reconfigurable Processor  
Keyword(2) Pipeline structure  
Keyword(3) Vector instruction  
1st Author's Name Toru Katagiri  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Hideharu Amano  
2nd Author's Affiliation Keio University (Keio Univ.)
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Date Time 2014-01-29 10:25:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-VLD2013-122,IEICE-CPSY2013-93,IEICE-RECONF2013-76 
Volume (vol) IEICE-113 
Number (no) no.416(VLD), no.417(CPSY), no.418(RECONF) 
Page pp.119-124 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-01-21,IEICE-CPSY-2014-01-21,IEICE-RECONF-2014-01-21 

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