Paper Abstract and Keywords |
Presentation |
2014-01-28 15:00
[Poster Presentation]
Low-Power 28nm FD-SOI SRAM for Image Processor Yuta Kawamoto, Shusuke Yoshimoto, Tomoki Nakagawa, Yuki Kitahara, Haruki Mori, Kenta Takagi, Shintaro Izumi (Kobe Univ.), Koji Nii (Renesas Electronics), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2013-116 Link to ES Tech. Rep. Archives: ICD2013-116 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent years, image recognition has been applied to various fields such as an automatic driving system. SRAM (Static Random Access Memory) is used as memory for image processing; a data amount and an area of the image processing memory on a chip are increasing with image resolution. The power consumption of the image processing memory is increasing as well. In a 65-nm process, the memory power occupies 43% in an image processor, and it comes to 60% in a 28-nm process. In particular, the feature of the low-power image processing memory is required for wearable electronics.
We propose a low-power SRAM for image processing. We will show SPICE simulation results using a 28-nm FD-SOI technology in the poster presentation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / Image Processor / FD-SOI / 28nm / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 419, ICD2013-116, pp. 41-41, Jan. 2014. |
Paper # |
ICD2013-116 |
Date of Issue |
2014-01-21 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2013-116 Link to ES Tech. Rep. Archives: ICD2013-116 |
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