Paper Abstract and Keywords |
Presentation |
2014-01-24 09:00
Frequency Response Analysis of Sub-us Response Digital Controller for POL Kenji Mii, Hirotaka Nonaka (Nagasaki Univ.), Daisuke Kanemoto (Yamanashi Univ.), Yoichi Ishizuka (Nagasaki Univ.) EE2013-39 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, the proposed hardware logic type digital controller for on-board SMPS which has a very small time-delay in control loop has been described. Some experimental has been done including evaluation of load current change and frequency characteristic of open loop transfer function. These results have been revealed that the proposed circuit could be suppressed the time delay to sub-11s excepting transition time of FET driver. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Digital controller / POL / DC-DC Converter / High speed response / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 392, EE2013-39, pp. 49-54, Jan. 2014. |
Paper # |
EE2013-39 |
Date of Issue |
2014-01-16 (EE) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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EE2013-39 |
Conference Information |
Committee |
EE |
Conference Date |
2014-01-23 - 2014-01-24 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
MIYAZAKI KANKO HOTEL |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
EE |
Conference Code |
2014-01-EE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Frequency Response Analysis of Sub-us Response Digital Controller for POL |
Sub Title (in English) |
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Digital controller |
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POL |
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DC-DC Converter |
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High speed response |
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1st Author's Name |
Kenji Mii |
1st Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
2nd Author's Name |
Hirotaka Nonaka |
2nd Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
3rd Author's Name |
Daisuke Kanemoto |
3rd Author's Affiliation |
Yamanashi University (Yamanashi Univ.) |
4th Author's Name |
Yoichi Ishizuka |
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Nagasaki University (Nagasaki Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-01-24 09:00:00 |
Presentation Time |
25 minutes |
Registration for |
EE |
Paper # |
EE2013-39 |
Volume (vol) |
vol.113 |
Number (no) |
no.392 |
Page |
pp.49-54 |
#Pages |
6 |
Date of Issue |
2014-01-16 (EE) |