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| Presentation | 2014-01-24 13:40 Comparison of the final addition circuit in SFQ parallel multiplier with a tree structure partial product adder circuit Akifumi Yamada, Takeshi Onomi, Koji Nakajima (Tohoku Univ.)  SCE2013-52 Link to ES Tech. Rep. Archives: SCE2013-52 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A single flux quantum (SFQ) circuit is capable of high-speed operation in a few 10 GHz, and it has a big advantage compared to the semiconductor circuit about calorific power. We have the goal of creating a high-speed multiplier significantly related to its performance in a fast Fourier transform circuit. Those of bit-serial type have been already developed[1],we are challenging the development of bit parallel type to take advantage of the high speed of the SFQ circuit. To speed up the parallel multiplier, the partial product generation, the partial product summation, and the configuration of the final-stage adder circuit should be studied. We investigate the final-stage adder circuit to achieve a faster and low power multi-plier. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Single Flux Quantum / Parallel multiplier / DaddaTree / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 401, SCE2013-52, pp. 101-104, Jan. 2014. | |
| Paper # | SCE2013-52 | |
| Date of Issue | 2014-01-16 (SCE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SCE2013-52 Link to ES Tech. Rep. Archives: SCE2013-52 |
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| Conference Information | |
| Committee | SCE |
| Conference Date | 2014-01-23 - 2014-01-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikaishinkou-kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Thin film, device technologies and their applications, etc. |
| Paper Information | |
| Registration To | SCE |
| Conference Code | 2014-01-SCE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Comparison of the final addition circuit in SFQ parallel multiplier with a tree structure partial product adder circuit |
| Sub Title (in English) | |
| Keyword(1) | Single Flux Quantum |
| Keyword(2) | Parallel multiplier |
| Keyword(3) | DaddaTree |
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| 1st Author's Name | Akifumi Yamada |
| 1st Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 2nd Author's Name | Takeshi Onomi |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | Koji Nakajima |
| 3rd Author's Affiliation | Tohoku University (Tohoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-01-24 13:40:00 |
| Presentation Time | 25 minutes |
| Registration for | SCE |
| Paper # | SCE2013-52 |
| Volume (vol) | vol.113 |
| Number (no) | no.401 |
| Page | pp.101-104 |
| #Pages | 4 |
| Date of Issue | 2014-01-16 (SCE) |
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