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Paper Abstract and Keywords
Presentation 2014-01-16 10:55
Novel Millimeter-wave PLL Synthesizer with Cascaded Phase Detectors
Hiroshi Matsumura, Yoichi Kawano, Masaru Sato, Takenori Ohshima, Toshihiro Shimura, Toshihide Suzuki, Yoji Ohashi (Fujitsu), Naoki Hara (Fujitsu Lab.) ED2013-114 MW2013-179 Link to ES Tech. Rep. Archives: ED2013-114 MW2013-179
Abstract (in Japanese) (See Japanese page) 
(in English) We present a novel millimeter-wave PLL architecture with cascaded phase detectors. It realizes low phase noise and low spurious characteristics concurrently. The 79-GHz band PLL synthesizer with the proposed architecture is developed in 65-nm CMOS technology. It achieves a phase noise of -90.0 dBc/Hz at 1 MHz offset and a normalized phase noise of -231.2 dBc/Hz2 at 1 MHz offset with a 49-MHz on-chip reference oscillator. It exhibits lower reference spurs of -29.3 dBc at 49 MHz and -36.0 dBc at 98 MHz.
Keyword (in Japanese) (See Japanese page) 
(in English) Phase locked loops / Phase detection / Phase noise / Millimeter-wave integrated circuits / CMOS integrated circuits / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 378, ED2013-114, pp. 25-28, Jan. 2014.
Paper # ED2013-114 
Date of Issue 2014-01-09 (ED, MW) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2013-114 MW2013-179 Link to ES Tech. Rep. Archives: ED2013-114 MW2013-179

Conference Information
Committee ED MW  
Conference Date 2014-01-16 - 2014-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Power devices, High-speed and high-frequency devices, Microwave Technologies, etc. 
Paper Information
Registration To ED 
Conference Code 2014-01-ED-MW 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Novel Millimeter-wave PLL Synthesizer with Cascaded Phase Detectors 
Sub Title (in English)  
Keyword(1) Phase locked loops  
Keyword(2) Phase detection  
Keyword(3) Phase noise  
Keyword(4) Millimeter-wave integrated circuits  
Keyword(5) CMOS integrated circuits  
1st Author's Name Hiroshi Matsumura  
1st Author's Affiliation Fujitsu Limited (Fujitsu)
2nd Author's Name Yoichi Kawano  
2nd Author's Affiliation Fujitsu Limited (Fujitsu)
3rd Author's Name Masaru Sato  
3rd Author's Affiliation Fujitsu Limited (Fujitsu)
4th Author's Name Takenori Ohshima  
4th Author's Affiliation Fujitsu Limited (Fujitsu)
5th Author's Name Toshihiro Shimura  
5th Author's Affiliation Fujitsu Limited (Fujitsu)
6th Author's Name Toshihide Suzuki  
6th Author's Affiliation Fujitsu Limited (Fujitsu)
7th Author's Name Yoji Ohashi  
7th Author's Affiliation Fujitsu Limited (Fujitsu)
8th Author's Name Naoki Hara  
8th Author's Affiliation Fujitsu Laboratories Ltd. (Fujitsu Lab.)
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Date Time 2014-01-16 10:55:00 
Presentation Time 25 
Registration for ED 
Paper # IEICE-ED2013-114,IEICE-MW2013-179 
Volume (vol) IEICE-113 
Number (no) no.378(ED), no.379(MW) 
Page pp.25-28 
#Pages IEICE-4 
Date of Issue IEICE-ED-2014-01-09,IEICE-MW-2014-01-09 

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