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| Presentation | 2013-12-13 11:20 Design and development of Gate Array using Poly-Si TFT Masashi Inoue, Tokiyoshi Matsuda, Mutsumi Kimura (Ryukoku Univ.)  SDM2013-123 Link to ES Tech. Rep. Archives: SDM2013-123 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this study, we performed the design and development of gate arrays using poly-Si TFTs. We designed and evaluated the gate arrays with implemented complementary inverter, NAND and NOR circuits. We fabricated the half adder and decoder using the gate arrays, and we confirmed actually working. In addition, we also compared the dynamic characteristics of the half adder using the gate array and normal half adder. It was found that the half adder using the gate array can be used to a higher frequency. This result is currently under consideration. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Poly-Si / Thin Film Transistor / Gate Array / HALF ADDER / DECODER / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 351, SDM2013-123, pp. 43-47, Dec. 2013. | |
| Paper # | SDM2013-123 | |
| Date of Issue | 2013-12-06 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2013-123 Link to ES Tech. Rep. Archives: SDM2013-123 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2013-12-13 - 2013-12-13 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NAIST |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Fabrication and Characterization of Si related materials |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2013-12-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and development of Gate Array using Poly-Si TFT |
| Sub Title (in English) | |
| Keyword(1) | Poly-Si |
| Keyword(2) | Thin Film Transistor |
| Keyword(3) | Gate Array |
| Keyword(4) | HALF ADDER |
| Keyword(5) | DECODER |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masashi Inoue |
| 1st Author's Affiliation | Ryukoku University (Ryukoku Univ.) |
| 2nd Author's Name | Tokiyoshi Matsuda |
| 2nd Author's Affiliation | Ryukoku University (Ryukoku Univ.) |
| 3rd Author's Name | Mutsumi Kimura |
| 3rd Author's Affiliation | Ryukoku University (Ryukoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-12-13 11:20:00 |
| Presentation Time | 20 minutes |
| Registration for | SDM |
| Paper # | SDM2013-123 |
| Volume (vol) | vol.113 |
| Number (no) | no.351 |
| Page | pp.43-47 |
| #Pages | 5 |
| Date of Issue | 2013-12-06 (SDM) |
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