Paper Abstract and Keywords |
Presentation |
2013-12-13 13:25
Variable Test-Timing Generation for Built-In Self-Test on FPGA Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Application-dependent test for FPGA targets quality improvement in silicon debug or online test; however, as it requires reconfigurations for design for testability, it is difficult to test the original path delay. To tackle this problem, the authors propose a test method that measures the fastest operating speed of the circuit using variable test timing. The paper proposes a variable test-timing generation method that utilizes embedded phase-shift function of PLL. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Built-In Self-Test / Variable test-timing / PLL / Phase-shift / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 353, DC2013-69, pp. 7-12, Dec. 2013. |
Paper # |
DC2013-69 |
Date of Issue |
2013-12-06 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2013-69 |
Conference Information |
Committee |
DC |
Conference Date |
2013-12-13 - 2013-12-13 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Safety, etc. |
Paper Information |
Registration To |
DC |
Conference Code |
2013-12-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Variable Test-Timing Generation for Built-In Self-Test on FPGA |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
Built-In Self-Test |
Keyword(3) |
Variable test-timing |
Keyword(4) |
PLL |
Keyword(5) |
Phase-shift |
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1st Author's Name |
Yasuo Sato |
1st Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
2nd Author's Name |
Munehiro Matsuura |
2nd Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
3rd Author's Name |
Hitoshi Arakawa |
3rd Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
4th Author's Name |
Yousuke Miyake |
4th Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
5th Author's Name |
Seiji Kajihara |
5th Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
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Speaker |
Author-1 |
Date Time |
2013-12-13 13:25:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
DC2013-69 |
Volume (vol) |
vol.113 |
Number (no) |
no.353 |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2013-12-06 (DC) |
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