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Paper Abstract and Keywords
Presentation 2013-11-29 10:30
A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing
Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2013-68
Abstract (in Japanese) (See Japanese page) 
(in English) High-Level Synthesis (HLS) has been utilized as a practical tool especially for designing Field Programmable
Gate Arrays (FPGAs). Complicated scientific applications can be relatively easily designed with HLS for high performance
computation. However, compared with other accelerators, size limitation of an FPGA is severe problem. In order to implement
a large algorithm, a large system with multiple FPGAs are required. Unfortunately, the current HLS tool has almost no
support to implement a large application into multiple FPGAs, and users must take care of it by themselves. In this report,
a design environment is proposed to divide a large algorithm into some small functions, and implement on some FPGAs by
using an existing HLS tool called CWB (Cyber Work Bench). A practical application in physics is adopted and processed by
the proposed tool.
Keyword (in Japanese) (See Japanese page) 
(in English) High Level Synthesis / HLS / Multi FPGA / Circuit Division / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 324, CPSY2013-68, pp. 53-58, Nov. 2013.
Paper # CPSY2013-68 
Date of Issue 2013-11-20 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing 
Sub Title (in English)  
Keyword(1) High Level Synthesis  
Keyword(2) HLS  
Keyword(3) Multi FPGA  
Keyword(4) Circuit Division  
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1st Author's Name Daiki Kugami  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Takaaki Miyajima  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Hideharu Amano  
3rd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2013-11-29 10:30:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2013-68 
Volume (vol) vol.113 
Number (no) no.324 
Page pp.53-58 
#Pages
Date of Issue 2013-11-20 (CPSY) 


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