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Paper Abstract and Keywords
Presentation 2013-11-28 08:30
Soft-core microprocessor for small reconfigurable device
Yuichi Watanabe, Taisuke Yamamoto, Yuki Yoshida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2013-46
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a soft-core processor implemented by using hardware description language that is
possible to be implemented on small recon gurable devices. The design goal of the proposed soft-core processor is
to minimize the resource usage when mapped on the recon gurable devices by adopting bit-serial architecture, not
only to increase the processing speed, but also to minimize it. This paper also evaluates the resource usages and
processing speed of the proposed soft-core processors, and compares the results between other soft-core processor
with small resource usages.
Keyword (in Japanese) (See Japanese page) 
(in English) soft-core CPU / soft-core IP / PLD / FPGA / architecture / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 325, RECONF2013-46, pp. 39-44, Nov. 2013.
Paper # RECONF2013-46 
Date of Issue 2013-11-20 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2013-46

Conference Information
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Soft-core microprocessor for small reconfigurable device 
Sub Title (in English)  
Keyword(1) soft-core CPU  
Keyword(2) soft-core IP  
Keyword(3) PLD  
Keyword(4) FPGA  
Keyword(5) architecture  
1st Author's Name Yuichi Watanabe  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Taisuke Yamamoto  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Yuki Yoshida  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Kazuya Tanigawa  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
5th Author's Name Tetsuo Hironaka  
5th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Date Time 2013-11-28 08:30:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2013-46 
Volume (vol) IEICE-113 
Number (no) no.325 
Page pp.39-44 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2013-11-20 

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