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| Presentation | 2013-11-28 09:45 An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2013-79 DC2013-45 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average interconnection delays are becoming serious issues. The fault-secure design technique which utilizes concurrent error detection is one of the approaches to overcome reliability degradation, and we can design systems based on trade-off between reliability and several kinds of overhead by giving a partial redundancy to operations. In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures. Our proposed algorithm receives a fixed area constraint and various time constrains as inputs, and aims at maximizing reliability under them. Experimental results demonstrate that our algorithm improves reliability by up to 44% with zero time and area overhead compared with the conventional approach. They also show that we can realize complete duplication of operations with zero area overhead and about 50% time overhead. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | high-level synthesis / fault-secure / concurrent error detection / partial redundancy / RDR architecture / interconnection delays / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 320, VLD2013-79, pp. 129-134, Nov. 2013. | |
| Paper # | VLD2013-79 | |
| Date of Issue | 2013-11-20 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-79 DC2013-45 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2013-11-27 - 2013-11-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2013 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | fault-secure |
| Keyword(3) | concurrent error detection |
| Keyword(4) | partial redundancy |
| Keyword(5) | RDR architecture |
| Keyword(6) | interconnection delays |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazushi Kawamura |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Masao Yanagisawa |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-11-28 09:45:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-79, DC2013-45 |
| Volume (vol) | vol.113 |
| Number (no) | no.320(VLD), no.321(DC) |
| Page | pp.129-134 |
| #Pages | 6 |
| Date of Issue | 2013-11-20 (VLD, DC) |
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