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Paper Abstract and Keywords
Presentation 2013-11-28 10:00
ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length
Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2013-49
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose an ILP-based method for simultaneous optimal technology mapping, placement and routing for programmable logic devices, such as FPGAs.
In general, for each of technology mapping, placement and routing, heuristic methods are used to obtain high quality solutions within a practical time. However, solution quality is not guaranteed, and the separated design processes (i.e., technology mapping, placement and routing) probably make the final solutions not optimal.
Thus, simultaneous and optimal methods are useful to evaluate and develop heuristic methods even if they take a long time.
In experiments, we confirmed that the optimal total wire length and critical path length of small circuits were obtained by our method.
Keyword (in Japanese) (See Japanese page) 
(in English) PLD / FPGA / technology mapping / placement and routing / exact optimal solution / ILP / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 325, RECONF2013-49, pp. 57-62, Nov. 2013.
Paper # RECONF2013-49 
Date of Issue 2013-11-20 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2013-49

Conference Information
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length 
Sub Title (in English)  
Keyword(1) PLD  
Keyword(2) FPGA  
Keyword(3) technology mapping  
Keyword(4) placement and routing  
Keyword(5) exact optimal solution  
Keyword(6) ILP  
1st Author's Name Hiroki Nishiyama  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Masato Inagi  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Shinobu Nagayama  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Shin'ichi Wakabayashi  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Date Time 2013-11-28 10:00:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2013-49 
Volume (vol) IEICE-113 
Number (no) no.325 
Page pp.57-62 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2013-11-20 

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