Paper Abstract and Keywords |
Presentation |
2013-11-27 14:30
Fault-Tolerant Design with Less Overhead than DMR Atsushi Matsuo, Shigeru Yamashita (Ritsumeikan Univ.) VLD2013-66 DC2013-32 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper proposes two methods to increase yeild by using Partially-Programmable Circuits (PPCs)
that are proposed to increase yeild recently. In our proposed methods, we add MUXs, LUTs and multipule re-
dundant connections into a PPC to bypass a fault. To realize our proposed methods, we develop a new concept
called Remaining SPFD. Remaining SPFD can be considered as an extension of SPFDs whhich are used to represent
functional
exibilities for LUT networks. Compared to Dual Module Redundancy (DMR), our proposed methods do
not duplicate an entire circuit. Therefore our proposed methods can realize fault-tolerant circuits with less overhead
than DMR. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
PPC / Fault Toreance / DMR / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 320, VLD2013-66, pp. 33-37, Nov. 2013. |
Paper # |
VLD2013-66 |
Date of Issue |
2013-11-20 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2013-66 DC2013-32 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2013-11-27 - 2013-11-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
|
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2013 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Fault-Tolerant Design with Less Overhead than DMR |
Sub Title (in English) |
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Keyword(1) |
PPC |
Keyword(2) |
Fault Toreance |
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DMR |
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1st Author's Name |
Atsushi Matsuo |
1st Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
2nd Author's Name |
Shigeru Yamashita |
2nd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-11-27 14:30:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2013-66, DC2013-32 |
Volume (vol) |
vol.113 |
Number (no) |
no.320(VLD), no.321(DC) |
Page |
pp.33-37 |
#Pages |
5 |
Date of Issue |
2013-11-20 (VLD, DC) |
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