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| Presentation | 2013-11-27 08:50 Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC Wataru Yoshimura, Kenichi Ohhata (Kagoshima Univ.)  CPM2013-108 ICD2013-85 Link to ES Tech. Rep. Archives: CPM2013-108 ICD2013-85 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A resistor ladder is an important circuit block for the parallel architecture analog-to-digital converters (ADCs). The output of ADC suffers from the distortion due to the kickback noise of comparators when the bias current of the resistor ladder is reduced to reduce its power dissipation. A distortion compensation technique which cancels the kickback noise by injecting the compensation current to the resistor ladder was proposed to overcome this problem. This technique, however, did not consider that the kickback noise depends on a sampling frequency and a variability of the resistor. Therefore, we propose an automatic distortion compensation circuit which detects the amount of the kickback noise and adjusts the compensation current properly. The simulation results demonstrated that the distortion can be reduced by proposed technique even when the sampling frequency change and the deviation in the resistor occurred. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | AD converter / resistor ladder / automatic distortion compensation technique / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 323, ICD2013-85, pp. 1-6, Nov. 2013. | |
| Paper # | ICD2013-85 | |
| Date of Issue | 2013-11-20 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPM2013-108 ICD2013-85 Link to ES Tech. Rep. Archives: CPM2013-108 ICD2013-85 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2013-11-27 - 2013-11-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2013 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC |
| Sub Title (in English) | |
| Keyword(1) | AD converter |
| Keyword(2) | resistor ladder |
| Keyword(3) | automatic distortion compensation technique |
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| 1st Author's Name | Wataru Yoshimura |
| 1st Author's Affiliation | Kagoshima University (Kagoshima Univ.) |
| 2nd Author's Name | Kenichi Ohhata |
| 2nd Author's Affiliation | Kagoshima University (Kagoshima Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-11-27 08:50:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | CPM2013-108, ICD2013-85 |
| Volume (vol) | vol.113 |
| Number (no) | no.322(CPM), no.323(ICD) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2013-11-20 (CPM, ICD) |
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