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| Presentation | 2013-11-27 15:20 A controller design in high-level synthesis for multi-cycle transient fault tolerance Yutaro Ishimori, Tatsuya Nakaso, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  VLD2013-68 DC2013-34 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This work discusses a design of the controller in a multi-cycle transient fault tolerant system. It focuses especially on the control signal generator, which is a component of the controller feeding control signals to the datapath in the system, and presents a method of logic simplification that utilizes the error detection/correction ability of the datapath. Case studies show that the proposed method can make controllers fault-tolerable with small area overhead compared with the conventional method based on triple modular redundancy. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Multi-cycle transient fault / high-level synthesis / controller synthesis / error correction/detection / logic simplification / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 321, DC2013-34, pp. 45-50, Nov. 2013. | |
| Paper # | DC2013-34 | |
| Date of Issue | 2013-11-20 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-68 DC2013-34 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2013-11-27 - 2013-11-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2013 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A controller design in high-level synthesis for multi-cycle transient fault tolerance |
| Sub Title (in English) | |
| Keyword(1) | Multi-cycle transient fault |
| Keyword(2) | high-level synthesis |
| Keyword(3) | controller synthesis |
| Keyword(4) | error correction/detection |
| Keyword(5) | logic simplification |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yutaro Ishimori |
| 1st Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 2nd Author's Name | Tatsuya Nakaso |
| 2nd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 3rd Author's Name | Tsuyoshi Iwagaki |
| 3rd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 4th Author's Name | Hideyuki Ichihara |
| 4th Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 5th Author's Name | Tomoo Inoue |
| 5th Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-11-27 15:20:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2013-68, DC2013-34 |
| Volume (vol) | vol.113 |
| Number (no) | no.320(VLD), no.321(DC) |
| Page | pp.45-50 |
| #Pages | 6 |
| Date of Issue | 2013-11-20 (VLD, DC) |
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