Paper Abstract and Keywords |
Presentation |
2013-11-27 13:25
A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.) CPM2013-116 ICD2013-93 Link to ES Tech. Rep. Archives: CPM2013-116 ICD2013-93 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, a design methodology for realizing power efficient nonvolatile FPGA (NVFPGA) using magnetic tunnel junction (MTJ) devices is discussed. Since circuit information in the NVFPGA remains without power supply, wasted standby power is eliminated. The relationship between the ultra low-power standby capability and MTJ read/write access power are discussed. As a typical application, an adder with a register is implemented on the proposed NVFPGA, which results in a total power reduction of 62 % compared to that of an SRAM-based FPGA. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / MTJ device / Power gating / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 323, ICD2013-93, pp. 49-53, Nov. 2013. |
Paper # |
ICD2013-93 |
Date of Issue |
2013-11-20 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
CPM2013-116 ICD2013-93 Link to ES Tech. Rep. Archives: CPM2013-116 ICD2013-93 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2013-11-27 - 2013-11-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2013 -New Field of VLSI Design- |
Paper Information |
Registration To |
ICD |
Conference Code |
2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA |
Sub Title (in English) |
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Keyword(1) |
FPGA |
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MTJ device |
Keyword(3) |
Power gating |
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1st Author's Name |
Daisuke Suzuki |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Masanori Natsui |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Akira Mochizuki |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
4th Author's Name |
Takahiro Hanyu |
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Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-11-27 13:25:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
CPM2013-116, ICD2013-93 |
Volume (vol) |
vol.113 |
Number (no) |
no.322(CPM), no.323(ICD) |
Page |
pp.49-53 |
#Pages |
5 |
Date of Issue |
2013-11-20 (CPM, ICD) |
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