Paper Abstract and Keywords |
Presentation |
2013-11-27 14:30
New Via Programmable Architecture VPEX4 (1)
-- Development of new logic element for improvement of routability and power consumption -- Ryohei Hori, Taku Otani, Tatsuro Hitomi, Shota Ueguchi (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-71 DC2013-37 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The Non-Recruring Engineering (NRE) cost of LSI is increasing drastically with the advances in LSI process and manufacturing technology. For this problem, we discuss using “Via programmable” technology which is programmed only via layer in photo-mask layer. We previously reported that proposal and evaluation of VPEX3 architecture configured logic function by costuming three via layers. In this paper, VPEX4 architecture is proposed as an improvement of VPEX3. In this result of the improvement, the area utilization of VPEX4 is better than that of VPEX3. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Structured ASIC / Via Programmable / Via Configurable / Exclusive-OR / Middle-volume production / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 320, VLD2013-71, pp. 81-86, Nov. 2013. |
Paper # |
VLD2013-71 |
Date of Issue |
2013-11-20 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2013-71 DC2013-37 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2013-11-27 - 2013-11-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
|
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2013 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
New Via Programmable Architecture VPEX4 (1) |
Sub Title (in English) |
Development of new logic element for improvement of routability and power consumption |
Keyword(1) |
Structured ASIC |
Keyword(2) |
Via Programmable |
Keyword(3) |
Via Configurable |
Keyword(4) |
Exclusive-OR |
Keyword(5) |
Middle-volume production |
Keyword(6) |
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Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Ryohei Hori |
1st Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
2nd Author's Name |
Taku Otani |
2nd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
3rd Author's Name |
Tatsuro Hitomi |
3rd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
4th Author's Name |
Shota Ueguchi |
4th Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
5th Author's Name |
Masaya Yoshikawa |
5th Author's Affiliation |
Meijo University (Meijo Univ.) |
6th Author's Name |
Takeshi Fujino |
6th Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-11-27 14:30:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2013-71, DC2013-37 |
Volume (vol) |
vol.113 |
Number (no) |
no.320(VLD), no.321(DC) |
Page |
pp.81-86 |
#Pages |
6 |
Date of Issue |
2013-11-20 (VLD, DC) |
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