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| Presentation | 2013-10-07 11:20 Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo)  VLD2013-48 ICD2013-72 IE2013-48 Link to ES Tech. Rep. Archives: ICD2013-72 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inherent robustness. However design flow for the circuit have not been automated. We propose synthe- sizing a synchronous gate level description from RTL description by a commercial logic synthesis tool and converting to self synchronous circuit. Also we designed a standard cell library of self synchronous circuit and performed place and route. Post-layout simulation was shown. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | dual pipeline / self synchronous / automated design flow / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 235, VLD2013-48, pp. 13-18, Oct. 2013. | |
| Paper # | VLD2013-48 | |
| Date of Issue | 2013-09-30 (VLD, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-48 ICD2013-72 IE2013-48 Link to ES Tech. Rep. Archives: ICD2013-72 |
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| Conference Information | |
| Committee | IE ICD VLD IPSJ-SLDM |
| Conference Date | 2013-10-07 - 2013-10-08 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2013-10-IE-ICD-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit |
| Sub Title (in English) | |
| Keyword(1) | dual pipeline |
| Keyword(2) | self synchronous |
| Keyword(3) | automated design flow |
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| 1st Author's Name | Atsushi Ito |
| 1st Author's Affiliation | The University of Tokyo (Univ. of Tokyo) |
| 2nd Author's Name | Makoto Ikeda |
| 2nd Author's Affiliation | The University of Tokyo (Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2013-10-07 11:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-48, ICD2013-72, IE2013-48 |
| Volume (vol) | vol.113 |
| Number (no) | no.235(VLD), no.236(ICD), no.237(IE) |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2013-09-30 (VLD, ICD, IE) |
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