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| Presentation | 2013-09-26 12:40 Efficient Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method Daisei Nagata, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)  CAS2013-36 NLP2013-48 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this report, we apply the block latency insertion method (block-LIM) to the transient analysis of on-chip power distribution networks (PDNs) with power/ground through silicon vias (P/G TSVs).The block-LIM has been proposed as a fast circuit simulation approach for large networks including a number of coupling elements such as mutual inductances and mutual capacitances. The block-LIM can simulate the on-chip PDNs with P/G TSVs, because they are modeled as equivalent circuits including mutual coupling elements. Numerical results show that the block-LIM can reduce the computational cost compared with HSPICE in the simulation of the equivalent circuit of the on-chip PDN with the P/G TSVs. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | block latency insertion method (block-LIM) / latency insertion method (LIM) / power/ground through silicon via (P/G TSV) / three-dimensional stacked on-chip power distribution network (PDN) / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 224, CAS2013-36, pp. 1-6, Sept. 2013. | |
| Paper # | CAS2013-36 | |
| Date of Issue | 2013-09-19 (CAS, NLP) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2013-36 NLP2013-48 |
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| Conference Information | |
| Committee | CAS NLP |
| Conference Date | 2013-09-26 - 2013-09-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus, Gifu University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | General |
| Paper Information | |
| Registration To | CAS |
| Conference Code | 2013-09-CAS-NLP |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Efficient Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method |
| Sub Title (in English) | |
| Keyword(1) | block latency insertion method (block-LIM) |
| Keyword(2) | latency insertion method (LIM) |
| Keyword(3) | power/ground through silicon via (P/G TSV) |
| Keyword(4) | three-dimensional stacked on-chip power distribution network (PDN) |
| Keyword(5) | |
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| 1st Author's Name | Daisei Nagata |
| 1st Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
| 2nd Author's Name | Tadatoshi Sekine |
| 2nd Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
| 3rd Author's Name | Hideki Asai |
| 3rd Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-09-26 12:40:00 |
| Presentation Time | 25 minutes |
| Registration for | CAS |
| Paper # | CAS2013-36, NLP2013-48 |
| Volume (vol) | vol.113 |
| Number (no) | no.224(CAS), no.225(NLP) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2013-09-19 (CAS, NLP) |
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