Paper Abstract and Keywords |
Presentation |
2013-09-19 09:25
A LUT Architecture Based on Partial Function of Shannon Expansion Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-27 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In order to implement logic functions, conventional eld programmable gate arrays (FPGAs) employs look-up tables (LUTs) as programmable logic cells. N-input LUTs can implement any N-input logic functions.However, LUT need many circuit resources to constitute. In this paper, we propose SLM based on the feature of Shannon Expansion. The experimental results show that the area in 7-SLM is 18% smaller than that in 7-LUT and the area in 8-SLM is 28% smaller than that in 8-LUT. 7-SLM provide the best area-delay product in all LUTs and SLMs. Further, the total number of conguration memory bits in 7-SLM is 31% smaller than the number of coniguration memory bits in 7-LUT. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / logic cell / LUT / Shannon Expansion / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 221, RECONF2013-27, pp. 43-48, Sept. 2013. |
Paper # |
RECONF2013-27 |
Date of Issue |
2013-09-11 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2013-27 |
Conference Information |
Committee |
RECONF |
Conference Date |
2013-09-18 - 2013-09-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Japan Advanced Institute of Science and Technology |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2013-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A LUT Architecture Based on Partial Function of Shannon Expansion |
Sub Title (in English) |
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Keyword(1) |
FPGA |
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logic cell |
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LUT |
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Shannon Expansion |
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1st Author's Name |
Kyosei Yanagida |
1st Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
2nd Author's Name |
Motoki Amagasaki |
2nd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
3rd Author's Name |
Masahiro Iida |
3rd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
4th Author's Name |
Morihiro Kuga |
4th Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
5th Author's Name |
Toshinori Sueyoshi |
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Kumamoto University (Kumamoto Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-09-19 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2013-27 |
Volume (vol) |
vol.113 |
Number (no) |
no.221 |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2013-09-11 (RECONF) |
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