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| Presentation | 2013-09-19 09:50 Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD Yuki Yoshida, Takumi Michida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN)  RECONF2013-28 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Reconfigurable device Memory-based Programmable Logic Device (MPLD) consists of an array of Multiple Look Up Table (MLUT) which are the basic element of MPLD. So, reducing the area of the MLUT is important in order to reduce the area of the MPLD. The goal of this paper is to reduce the circuit area of the decoder, which is easy to modify, that accounts for 20% percent of MPLD area. As a technique for reducing the circuit area the pass transistor logic was used for decoder implementation. On the evaluation result by the total transistor area, the decoder design with the pass transistor logic was decreased to 62% and 53% by the tree type decoder design, the 5 input NOR gates design respectively. From the result, we have shown the possibility of the layout area reduction in MLUT by designing the decoder with the pass transistor logic technique. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | MPLD / PLD / FPGA / decoder / pass transistor logic / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 221, RECONF2013-28, pp. 49-54, Sept. 2013. | |
| Paper # | RECONF2013-28 | |
| Date of Issue | 2013-09-11 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2013-28 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2013-09-18 - 2013-09-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Japan Advanced Institute of Science and Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2013-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD |
| Sub Title (in English) | |
| Keyword(1) | MPLD |
| Keyword(2) | PLD |
| Keyword(3) | FPGA |
| Keyword(4) | decoder |
| Keyword(5) | pass transistor logic |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuki Yoshida |
| 1st Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 2nd Author's Name | Takumi Michida |
| 2nd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 3rd Author's Name | Kazuya Tanigawa |
| 3rd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 4th Author's Name | Tetsuo Hironaka |
| 4th Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 5th Author's Name | Kenichi Shimomai |
| 5th Author's Affiliation | TAIYO YUDEN CO,LTD. (TAIYO YUDEN) |
| 6th Author's Name | Takashi Ishiguro |
| 6th Author's Affiliation | TAIYO YUDEN CO,LTD. (TAIYO YUDEN) |
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| Speaker | Author-1 |
| Date Time | 2013-09-19 09:50:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2013-28 |
| Volume (vol) | vol.113 |
| Number (no) | no.221 |
| Page | pp.49-54 |
| #Pages | 6 |
| Date of Issue | 2013-09-11 (RECONF) |
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