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| Presentation | 2013-08-02 11:15 [Invited Talk] An LDPC Decoder with Time Domain Analog and Digital Mixed Signal Processing Daisuke Miyashita, Ryo Yamaki (Toshiba), Kazunori Hashiyoshi (Toshiba Microelectronics), Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa (Toshiba)  SDM2013-79 ICD2013-61 Link to ES Tech. Rep. Archives: SDM2013-79 ICD2013-61 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent multiple bits of information. We developed a time-domain analog and digital mixed-signal processing technique which employs time as analog quantity and is fully compatible with digital signal processing. We demonstrated the effectiveness of the technique by fabricating a test chip of a (32, 8) low-density parity-check code decoder in a 65 nm CMOS technology. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Analog computation / low-density parity-check code / LDPC / LDPC decoder / time-to-digital converter / TDC / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 173, ICD2013-61, pp. 71-76, Aug. 2013. | |
| Paper # | ICD2013-61 | |
| Date of Issue | 2013-07-25 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2013-79 ICD2013-61 Link to ES Tech. Rep. Archives: SDM2013-79 ICD2013-61 |
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| Conference Information | |
| Committee | SDM ICD |
| Conference Date | 2013-08-01 - 2013-08-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Low voltage/low power techniques, novel devices, circuits, and applications |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2013-08-SDM-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An LDPC Decoder with Time Domain Analog and Digital Mixed Signal Processing |
| Sub Title (in English) | |
| Keyword(1) | Analog computation |
| Keyword(2) | low-density parity-check code |
| Keyword(3) | LDPC |
| Keyword(4) | LDPC decoder |
| Keyword(5) | time-to-digital converter |
| Keyword(6) | TDC |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Daisuke Miyashita |
| 1st Author's Affiliation | Toshiba (Toshiba) |
| 2nd Author's Name | Ryo Yamaki |
| 2nd Author's Affiliation | Toshiba (Toshiba) |
| 3rd Author's Name | Kazunori Hashiyoshi |
| 3rd Author's Affiliation | Toshiba Microelectronics (Toshiba Microelectronics) |
| 4th Author's Name | Hiroyuki Kobayashi |
| 4th Author's Affiliation | Toshiba (Toshiba) |
| 5th Author's Name | Shouhei Kousai |
| 5th Author's Affiliation | Toshiba (Toshiba) |
| 6th Author's Name | Yukihito Oowaki |
| 6th Author's Affiliation | Toshiba (Toshiba) |
| 7th Author's Name | Yasuo Unekawa |
| 7th Author's Affiliation | Toshiba (Toshiba) |
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| Speaker | Author-1 |
| Date Time | 2013-08-02 11:15:00 |
| Presentation Time | 45 minutes |
| Registration for | ICD |
| Paper # | SDM2013-79, ICD2013-61 |
| Volume (vol) | vol.113 |
| Number (no) | no.172(SDM), no.173(ICD) |
| Page | pp.71-76 |
| #Pages | 6 |
| Date of Issue | 2013-07-25 (SDM, ICD) |
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