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Paper Abstract and Keywords
Presentation 2013-08-02 10:25
28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59 Link to ES Tech. Rep. Archives: SDM2013-77 ICD2013-59
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high-k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent highspeed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.
Keyword (in Japanese) (See Japanese page) 
(in English) 28nm / CMOS / Memory / Embedded ROM / 2T ROM bitcell / High speed / Low power source bias control /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 173, ICD2013-59, pp. 59-64, Aug. 2013.
Paper # ICD2013-59 
Date of Issue 2013-07-25 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Download PDF SDM2013-77 ICD2013-59 Link to ES Tech. Rep. Archives: SDM2013-77 ICD2013-59

Conference Information
Committee SDM ICD  
Conference Date 2013-08-01 - 2013-08-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Kanazawa University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To ICD 
Conference Code 2013-08-SDM-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique 
Sub Title (in English)  
Keyword(1) 28nm  
Keyword(2) CMOS  
Keyword(3) Memory  
Keyword(4) Embedded ROM  
Keyword(5) 2T ROM bitcell  
Keyword(6) High speed  
Keyword(7) Low power source bias control  
Keyword(8)  
1st Author's Name Yukiko Umemoto  
1st Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
2nd Author's Name Koji Nii  
2nd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
3rd Author's Name Jiro Ishikawa  
3rd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
4th Author's Name Makoto Yabuuchi  
4th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
5th Author's Name Yasumasa Tsukamoto  
5th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
6th Author's Name Shinji Tanaka  
6th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
7th Author's Name Koji Tanaka  
7th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
8th Author's Name Kazutaka Mori  
8th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
9th Author's Name Kazumasa Yanagisawa  
9th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
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Speaker
Date Time 2013-08-02 10:25:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2013-77,IEICE-ICD2013-59 
Volume (vol) IEICE-113 
Number (no) no.172(SDM), no.173(ICD) 
Page pp.59-64 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2013-07-25,IEICE-ICD-2013-07-25 


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