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Paper Abstract and Keywords
Presentation 2013-08-01 09:50
Scaling Strategy for Low Power RF Applications with Multi Gate Oxide Dual Work function (DWF) MOSFETs Utilizing Self-Aligned Integration Scheme
Toshitaka Miyata, Shigeru Kawanaka, Akira Hokazono, Tatsuya Ohguro, Yoshiaki Toyoshima (TOSHIBA) SDM2013-67 ICD2013-49 Link to ES Tech. Rep. Archives: SDM2013-67 ICD2013-49
Abstract (in Japanese) (See Japanese page) 
(in English) Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utilizing conventional CMOS platform process for the first time. Here, we obtained not only the improved transconductance (GM) and drain conductance (GD), but also the enlarged operation voltage window employing multi gate oxide structure combined with DWF-MOSFET gate stack. Also, the discriminative features of DWF-MOSFET operation were revealed by TCAD analysis indicating the potential ability of reduced power consumption for RF applications.
Keyword (in Japanese) (See Japanese page) 
(in English) RF transistor / Dual Work Function FET / DWF-FET / Multi Gate Oxide Dual Work Function / MGO-DWF-FET / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 172, SDM2013-67, pp. 13-18, Aug. 2013.
Paper # SDM2013-67 
Date of Issue 2013-07-25 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2013-67 ICD2013-49 Link to ES Tech. Rep. Archives: SDM2013-67 ICD2013-49

Conference Information
Committee SDM ICD  
Conference Date 2013-08-01 - 2013-08-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Kanazawa University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To SDM 
Conference Code 2013-08-SDM-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Scaling Strategy for Low Power RF Applications with Multi Gate Oxide Dual Work function (DWF) MOSFETs Utilizing Self-Aligned Integration Scheme 
Sub Title (in English)  
Keyword(1) RF transistor  
Keyword(2) Dual Work Function FET  
Keyword(3) DWF-FET  
Keyword(4) Multi Gate Oxide Dual Work Function  
Keyword(5) MGO-DWF-FET  
1st Author's Name Toshitaka Miyata  
1st Author's Affiliation TOSHIBA (TOSHIBA)
2nd Author's Name Shigeru Kawanaka  
2nd Author's Affiliation TOSHIBA (TOSHIBA)
3rd Author's Name Akira Hokazono  
3rd Author's Affiliation TOSHIBA (TOSHIBA)
4th Author's Name Tatsuya Ohguro  
4th Author's Affiliation TOSHIBA (TOSHIBA)
5th Author's Name Yoshiaki Toyoshima  
5th Author's Affiliation TOSHIBA (TOSHIBA)
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Date Time 2013-08-01 09:50:00 
Presentation Time 25 
Registration for SDM 
Paper # IEICE-SDM2013-67,IEICE-ICD2013-49 
Volume (vol) IEICE-113 
Number (no) no.172(SDM), no.173(ICD) 
Page pp.13-18 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2013-07-25,IEICE-ICD-2013-07-25 

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