Paper Abstract and Keywords |
Presentation |
2013-08-01 13:00
[Invited Talk]
Tera-Scale Three-Dimensional Integration (3DI) using Bumpless TSV Interconnects Takayuki Ohba (Tokyo Inst. of Tech.) SDM2013-70 ICD2013-52 Link to ES Tech. Rep. Archives: SDM2013-70 ICD2013-52 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In combination with 3D logic, memory, and cooling devices, it is possible to construct a roadmap towards high-density integration, low power consumption, and miniaturization of 3D chip-sets, especially next-generation logic-memory stacks for personal digital assistants (PDAs) such as Smartphones and high-end servers. Because wafer thinning to 10 m or less provides small features, it is possible to realize a total 3D stack height of less than 500 m, even after stacking seven dies. This satisfies current package standards. In addition, stacking 32 or more layers of 16 Gb/cm2 devices fabricated by 22 nm technology, which is two generations ahead, would achieve terabit (Tb) capacity. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Bumpless / Chip-on-Wafer / Wafer-on-Wafer / Thinning-First / Via-last after Bonding / Tera-Scale / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 172, SDM2013-70, pp. 29-30, Aug. 2013. |
Paper # |
SDM2013-70 |
Date of Issue |
2013-07-25 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2013-70 ICD2013-52 Link to ES Tech. Rep. Archives: SDM2013-70 ICD2013-52 |
Conference Information |
Committee |
SDM ICD |
Conference Date |
2013-08-01 - 2013-08-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kanazawa University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Low voltage/low power techniques, novel devices, circuits, and applications |
Paper Information |
Registration To |
SDM |
Conference Code |
2013-08-SDM-ICD |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Tera-Scale Three-Dimensional Integration (3DI) using Bumpless TSV Interconnects |
Sub Title (in English) |
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Keyword(1) |
Bumpless |
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Chip-on-Wafer |
Keyword(3) |
Wafer-on-Wafer |
Keyword(4) |
Thinning-First |
Keyword(5) |
Via-last after Bonding |
Keyword(6) |
Tera-Scale |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Takayuki Ohba |
1st Author's Affiliation |
Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
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Speaker |
Author-1 |
Date Time |
2013-08-01 13:00:00 |
Presentation Time |
45 minutes |
Registration for |
SDM |
Paper # |
SDM2013-70, ICD2013-52 |
Volume (vol) |
vol.113 |
Number (no) |
no.172(SDM), no.173(ICD) |
Page |
pp.29-30 |
#Pages |
2 |
Date of Issue |
2013-07-25 (SDM, ICD) |
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