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Paper Abstract and Keywords
Presentation 2013-07-12 09:40
Low Power Memory Based Design Method of Constant Multipliers for Digital Filters
Kosuke Kabasawa (Waseda Univ.), Tadahiko Sugibayashi (NEC), Masao Yanagisawa, Shinji Kimura (Waseda Univ.) CAS2013-19 VLD2013-29 SIP2013-49 MSS2013-19
Abstract (in Japanese) (See Japanese page) 
(in English) Digital Signal Processing of sounds and images are using many digital filters which conputes the summation of multiplications between a sequence of constats and a time sequence of an input.
In this manuscript, a memory based design method for such constant multiplication is described.
In the design, the trade-off between the size of a memory and that of the logic is considered, and its speed and power consumption is optimized.
The read power of a memory is independent with the output read from the memory and a memory can encapsulate the toggles of logic gates in gate-based designs.
By separating an input into several parts and designing such separated small multipliers using a memory, the memory size can be reduced drastically.
The proposed constant multiplier has been implemented on ASIC, and shows the power reduction compared with gate-level design.
Keyword (in Japanese) (See Japanese page) 
(in English) Memory-Based Design / Digital Filter / IIR Filter / FIR Filter / Input Separation for Multiplier / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 119, VLD2013-29, pp. 101-106, July 2013.
Paper # VLD2013-29 
Date of Issue 2013-07-04 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Download PDF CAS2013-19 VLD2013-29 SIP2013-49 MSS2013-19

Conference Information
Committee SIP CAS MSS VLD  
Conference Date 2013-07-11 - 2013-07-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System, signal processing and related topics 
Paper Information
Registration To VLD 
Conference Code 2013-07-SIP-CAS-MSS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low Power Memory Based Design Method of Constant Multipliers for Digital Filters 
Sub Title (in English)  
Keyword(1) Memory-Based Design  
Keyword(2) Digital Filter  
Keyword(3) IIR Filter  
Keyword(4) FIR Filter  
Keyword(5) Input Separation for Multiplier  
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Keyword(7)  
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1st Author's Name Kosuke Kabasawa  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Tadahiko Sugibayashi  
2nd Author's Affiliation NEC Corporation (NEC)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Shinji Kimura  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2013-07-12 09:40:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # CAS2013-19, VLD2013-29, SIP2013-49, MSS2013-19 
Volume (vol) vol.113 
Number (no) no.118(CAS), no.119(VLD), no.120(SIP), no.121(MSS) 
Page pp.101-106 
#Pages
Date of Issue 2013-07-04 (CAS, VLD, SIP, MSS) 


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