Paper Abstract and Keywords |
Presentation |
2013-07-11 18:00
SOM Based FPGA Placement Method Considering Wire Segment Length Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow.
Although nondeterministic algorithms such as SA(Simulated Annealing) algorithm are successful in solving this problem, they are known to be slow.
We have been introduced neural network approach which is a Kohonen SOM(Sefl Organizing feature Maps) to FPGA placement.
In this paper, we consider FPGA routing structure as output layer of SOM.
Two type FPGA structure, which are multi segment based homogeneous and hierarchical fault tolerant structure, are treated.
In this evaluation, though critical path delay of SOM only method are 27% slower than original VPR, execution time is 97% improved on average.
By contrast, critical path delay of SOM-SA hybrid method are 5% faster than original VPR, execution time is 27% improved on average. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA placement / Self-Organizing Maps / SOM / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 119, VLD2013-26, pp. 83-88, July 2013. |
Paper # |
VLD2013-26 |
Date of Issue |
2013-07-04 (CAS, VLD, SIP, MSS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 |
Conference Information |
Committee |
SIP CAS MSS VLD |
Conference Date |
2013-07-11 - 2013-07-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kumamoto Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System, signal processing and related topics |
Paper Information |
Registration To |
VLD |
Conference Code |
2013-07-SIP-CAS-MSS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
SOM Based FPGA Placement Method Considering Wire Segment Length |
Sub Title (in English) |
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Keyword(1) |
FPGA placement |
Keyword(2) |
Self-Organizing Maps |
Keyword(3) |
SOM |
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1st Author's Name |
Tetsuro Hamada |
1st Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
2nd Author's Name |
Motoki Amagasaki |
2nd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
3rd Author's Name |
Masahiro Iida |
3rd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
4th Author's Name |
Morihiro Kuga |
4th Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
5th Author's Name |
Toshinori Sueyoshi |
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Kumamoto University (Kumamoto Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-07-11 18:00:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
CAS2013-16, VLD2013-26, SIP2013-46, MSS2013-16 |
Volume (vol) |
vol.113 |
Number (no) |
no.118(CAS), no.119(VLD), no.120(SIP), no.121(MSS) |
Page |
pp.83-88 |
#Pages |
6 |
Date of Issue |
2013-07-04 (CAS, VLD, SIP, MSS) |
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