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| Presentation | 2013-07-05 17:40 Failure mode analysis for flip-flops at low voltages Takafumi Fujita, Junya Kawashima, Masayuki Hiromoto (Kyouto Univ.), Hiroshi Tsutsui (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Sato (Kyouto Univ.)  ICD2013-45 Link to ES Tech. Rep. Archives: ICD2013-45 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Towards the reducing power consumption, subthreshold circuit which operates at a low voltage below the threshold voltage of the transistor has been widely researched. The low power supply voltage circuits, variation for the minimum operation voltage which is defined by the minimum supply voltage that circuit is operable, and circuit design considering timing variation are important to obtain appropriate yield. In this paper, we focus on the flip-flop minimum operation voltage especially in the standard cells. Static failure modes are classified as a factor of the minimum operation voltage, and timing constraints are analyzed. By analyzing the failure modes,it will be possible to identify the logic circuit elements which are frangible in low supply voltage. In low supply voltage operation, as compared with the combination circuit, it was found that there is not need to assign many timing margin to sequential circuit. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Subthreshold circuit / minimum operation voltage / timing constraint / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 112, ICD2013-45, pp. 129-134, July 2013. | |
| Paper # | ICD2013-45 | |
| Date of Issue | 2013-06-27 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2013-45 Link to ES Tech. Rep. Archives: ICD2013-45 |
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| Conference Information | |
| Committee | ICD ITE-IST |
| Conference Date | 2013-07-04 - 2013-07-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | San Refre Hakodate |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface Circuitry |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2013-07-ICD-IST |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Failure mode analysis for flip-flops at low voltages |
| Sub Title (in English) | |
| Keyword(1) | Subthreshold circuit |
| Keyword(2) | minimum operation voltage |
| Keyword(3) | timing constraint |
| Keyword(4) | |
| Keyword(5) | |
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| 1st Author's Name | Takafumi Fujita |
| 1st Author's Affiliation | Kyouto University (Kyouto Univ.) |
| 2nd Author's Name | Junya Kawashima |
| 2nd Author's Affiliation | Kyouto University (Kyouto Univ.) |
| 3rd Author's Name | Masayuki Hiromoto |
| 3rd Author's Affiliation | Kyouto University (Kyouto Univ.) |
| 4th Author's Name | Hiroshi Tsutsui |
| 4th Author's Affiliation | Hokkaido University (Hokkaido Univ.) |
| 5th Author's Name | Hiroyuki Ochi |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 6th Author's Name | Takashi Sato |
| 6th Author's Affiliation | Kyouto University (Kyouto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-07-05 17:40:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2013-45 |
| Volume (vol) | vol.113 |
| Number (no) | no.112 |
| Page | pp.129-134 |
| #Pages | 6 |
| Date of Issue | 2013-06-27 (ICD) |
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