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| Presentation | 2013-07-04 09:30 93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage Inverter for Negative Resistance (MINR) in 0.7V, 9.2uW, 39MHz Crystal Oscillator Shunta Iguchi (Univ. of Tokyo), Akira Saito (STARC), Yunfei Zheng (Univ. of Tokyo), Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo)  ICD2013-24 Link to ES Tech. Rep. Archives: ICD2013-24 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In order to reduce the power consumption of a crystal oscillator (XO), an automatic self power gating (ASPG) and a multistage inverter for a negative resistance (MINR) are proposed. By combining ASPG and MINR, the measured power of a 39MHz XO in 40nm CMOS decreases by 93% from 139uW to 9.2uW, which is the lowest power in the published XO's at 0.7V. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Crystal oscillator / Automatic Self Power Gating / Multistage Inverter for Negative Resistance / Low power / Low voltage / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 112, ICD2013-24, pp. 1-6, July 2013. | |
| Paper # | ICD2013-24 | |
| Date of Issue | 2013-06-27 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2013-24 Link to ES Tech. Rep. Archives: ICD2013-24 |
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| Conference Information | |
| Committee | ICD ITE-IST |
| Conference Date | 2013-07-04 - 2013-07-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | San Refre Hakodate |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface Circuitry |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2013-07-ICD-IST |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage Inverter for Negative Resistance (MINR) in 0.7V, 9.2uW, 39MHz Crystal Oscillator |
| Sub Title (in English) | |
| Keyword(1) | Crystal oscillator |
| Keyword(2) | Automatic Self Power Gating |
| Keyword(3) | Multistage Inverter for Negative Resistance |
| Keyword(4) | Low power |
| Keyword(5) | Low voltage |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Shunta Iguchi |
| 1st Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
| 2nd Author's Name | Akira Saito |
| 2nd Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 3rd Author's Name | Yunfei Zheng |
| 3rd Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
| 4th Author's Name | Kazunori Watanabe |
| 4th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 5th Author's Name | Takayasu Sakurai |
| 5th Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
| 6th Author's Name | Makoto Takamiya |
| 6th Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2013-07-04 09:30:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2013-24 |
| Volume (vol) | vol.113 |
| Number (no) | no.112 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2013-06-27 (ICD) |
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