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Paper Abstract and Keywords
Presentation 2013-07-04 10:20
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near-Threshold Logic Circuits
Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) ICD2013-26 Link to ES Tech. Rep. Archives: ICD2013-26
Abstract (in Japanese) (See Japanese page) 
(in English) In order to eliminate the limitation of a narrow frequency range of conventional resonant clocking, intermittent resonant clocking (IRC) is proposed to enable power reduction at any clock frequency for near-threshold logic circuits. In a 0.37V 32-bit adder array in 40nm CMOS, compared with conventional non-resonant clocking, IRC with a proposed voltage doubler reduces the clock power by 36% at 980kHz and the clock leakage power by 81%.
Keyword (in Japanese) (See Japanese page) 
(in English) Extremely Low Power / Near-Threshold Circuit / Resonant Clocking / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 112, ICD2013-26, pp. 13-18, July 2013.
Paper # ICD2013-26 
Date of Issue 2013-06-27 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2013-26 Link to ES Tech. Rep. Archives: ICD2013-26

Conference Information
Committee ICD ITE-IST  
Conference Date 2013-07-04 - 2013-07-05 
Place (in Japanese) (See Japanese page) 
Place (in English) San Refre Hakodate 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface Circuitry 
Paper Information
Registration To ICD 
Conference Code 2013-07-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near-Threshold Logic Circuits 
Sub Title (in English)  
Keyword(1) Extremely Low Power  
Keyword(2) Near-Threshold Circuit  
Keyword(3) Resonant Clocking  
1st Author's Name Hiroshi Fuketa  
1st Author's Affiliation University of Tokyo (Univ. of Tokyo)
2nd Author's Name Masahiro Nomura  
2nd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
3rd Author's Name Makoto Takamiya  
3rd Author's Affiliation University of Tokyo (Univ. of Tokyo)
4th Author's Name Takayasu Sakurai  
4th Author's Affiliation University of Tokyo (Univ. of Tokyo)
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Date Time 2013-07-04 10:20:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-ICD2013-26 
Volume (vol) IEICE-113 
Number (no) no.112 
Page pp.13-18 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2013-06-27 

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