IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2013-06-21 14:15
A method of deterministic LFSR seed generation for scan-based BIST
Takanori Moriyasu, Satoshi Ohtake (Oita Univ.) DC2013-11
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a method of LFSR seed generation for LFSR reseeding of scan-based BIST of VLSI circuits. So far, a scan test pattern detecting some fault is first generated using an ATPG tool and the generated pattern is then converted into a seed. However, the conversion does not always succeed and the fault may not be detected. For a given circuit with scan-based BIST, the proposed method first creates a seed generation model for the circuit. The seed generation model consists of the combinational part of the circuit and the XOR network representing the logic functions of LFSR seed variables for scan flip-flops. LFSR seeds for faults are then generated as test patterns of the seed generation model by using an ATPG tool. In this paper, the effectiveness of the proposed method is shown by experiments using ITC'99 benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) Scan-based BIST / LFSR / reseeding / seed generation / test generation constraint / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 104, DC2013-11, pp. 7-12, June 2013.
Paper # DC2013-11 
Date of Issue 2013-06-14 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2013-11

Conference Information
Committee DC  
Conference Date 2013-06-21 - 2013-06-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design, Test, Verification 
Paper Information
Registration To DC 
Conference Code 2013-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A method of deterministic LFSR seed generation for scan-based BIST 
Sub Title (in English)  
Keyword(1) Scan-based BIST  
Keyword(2) LFSR  
Keyword(3) reseeding  
Keyword(4) seed generation  
Keyword(5) test generation constraint  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Takanori Moriyasu  
1st Author's Affiliation Oita University (Oita Univ.)
2nd Author's Name Satoshi Ohtake  
2nd Author's Affiliation Oita University (Oita Univ.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2013-06-21 14:15:00 
Presentation Time 30 minutes 
Registration for DC 
Paper # DC2013-11 
Volume (vol) vol.113 
Number (no) no.104 
Page pp.7-12 
#Pages
Date of Issue 2013-06-14 (DC) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan