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Paper Abstract and Keywords
Presentation 2013-06-21 13:45
A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches are to separate a controller and a data path by using scan design, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually degrades the testability. To resolve this problem, an approach that augments a controller by adding extra control functions to make a data path easily testable was proposed. However, the approach cannot always succeed in generating test sequences with high fault coverage if a general ATPG tool is used without knowing any information of augmented control functions. In this paper, we introduce “easily testable functional k-time expansion models for data paths” and propose a method for augmenting a controller such that easily testable functional k-time expansion models for the data path are generated. Experimental results show the effectiveness of the proposed method.
Keyword (in Japanese) (See Japanese page) 
(in English) non-scan testing / easily testable functional k-time expansion models / controller augmentation / sequential test generation / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 104, DC2013-10, pp. 1-6, June 2013.
Paper # DC2013-10 
Date of Issue 2013-06-14 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2013-06-21 - 2013-06-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design, Test, Verification 
Paper Information
Registration To DC 
Conference Code 2013-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits 
Sub Title (in English)  
Keyword(1) non-scan testing  
Keyword(2) easily testable functional k-time expansion models  
Keyword(3) controller augmentation  
Keyword(4) sequential test generation  
1st Author's Name Yusuke Kodama  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Jun Nishimaki  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Tetsuya Masuda  
3rd Author's Affiliation Nihon University (Nihon Univ)
4th Author's Name Toshinori Hosokawa  
4th Author's Affiliation Nihon University (Nihon Univ)
5th Author's Name Hideo Fujiwara  
5th Author's Affiliation Osaka Gakuin University (Osaka Gakuin Univ)
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Date Time 2013-06-21 13:45:00 
Presentation Time 30 
Registration for DC 
Paper # IEICE-DC2013-10 
Volume (vol) IEICE-113 
Number (no) no.104 
Page pp.1-6 
#Pages IEICE-6 
Date of Issue IEICE-DC-2013-06-14 

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