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| Presentation | 2013-05-21 11:25 A defect-robust FPGA-IP core architecture Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2013-13 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we propose fault-tolerant FPGA -IP cores for system LSI. Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are regular tile structure, spare modules and bypass wires for fault avoidance, and con guration mechanism for single-cycle recon guration. We also develop routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGA and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 2.2 times the area and 1.3 times the delay compared with conventional FPGA architectures. At the same time, conventional FPGAs cannot tolerate faults, whereas our architectures perform with a 90% success rate in fault avoidance for a ratio of faulty tiles of 1%. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA-IP core / dependable / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 52, RECONF2013-13, pp. 67-72, May 2013. | |
| Paper # | RECONF2013-13 | |
| Date of Issue | 2013-05-13 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2013-13 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2013-05-20 - 2013-05-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi Prefectural Culture Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2013-05-RECONF |
| Language | English (Japanese title is available) |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A defect-robust FPGA-IP core architecture |
| Sub Title (in English) | |
| Keyword(1) | FPGA-IP core |
| Keyword(2) | dependable |
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| 1st Author's Name | Motoki Amagasaki |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Kazuki Inoue |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Qian Zhao |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Morihiro Kuga |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 6th Author's Name | Toshinori Sueyoshi |
| 6th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-05-21 11:25:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2013-13 |
| Volume (vol) | vol.113 |
| Number (no) | no.52 |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2013-05-13 (RECONF) |
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