Paper Abstract and Keywords |
Presentation |
2013-04-11 14:20
[Invited Lecture]
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique
-- Achieves 1.0ns/200ps Wake-Up/Power-Off Times -- Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike (Tohoku Univ.), Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome (NEC), Shoji Ikeda, Takahiro Hanyu, Hideo Ohno (Tohoku Univ.) ICD2013-6 Link to ES Tech. Rep. Archives: ICD2013-6 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 1Mb embedded memory was designed and fabricated using a cell consisting of four NFETs and two spin-transfer torque magnetic tunnel junctions (STT-MTJs) which is a nonvolatile memory device with excellent write endurance. A 32b fine-grained power gating technique is applied to achieve a fast access/cycle times along with a low standby and operation powers. Since the 4T2MTJ cell size is defined by its four NFETs with the two MTJs put on them, the cell has a potential to become smaller than the SRAM cell. It was shown that the 4T2MTJ STT-RAM macro can be smaller than the SRAM counterpart by scaling the technology to 25nm-45nm and beyond, depending on its scaling scenarios, due to the MTJ switching current reduction by the scaling. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
STT-MTJ / STT-RAM / Power Gating / Static Noise Margin (SNM) / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 1, ICD2013-6, pp. 27-32, April 2013. |
Paper # |
ICD2013-6 |
Date of Issue |
2013-04-04 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2013-6 Link to ES Tech. Rep. Archives: ICD2013-6 |
Conference Information |
Committee |
ICD |
Conference Date |
2013-04-11 - 2013-04-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Advanced Industrial Science and Technology (AIST) |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Memory Device Technologies |
Paper Information |
Registration To |
ICD |
Conference Code |
2013-04-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique |
Sub Title (in English) |
Achieves 1.0ns/200ps Wake-Up/Power-Off Times |
Keyword(1) |
STT-MTJ |
Keyword(2) |
STT-RAM |
Keyword(3) |
Power Gating |
Keyword(4) |
Static Noise Margin (SNM) |
Keyword(5) |
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Keyword(6) |
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Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Tetsuo Endoh |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Takashi Ohsawa |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Hiroki Koike |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
4th Author's Name |
Sadahiko Miura |
4th Author's Affiliation |
NEC (NEC) |
5th Author's Name |
Hiroaki Honjo |
5th Author's Affiliation |
NEC (NEC) |
6th Author's Name |
Keiichi Tokutome |
6th Author's Affiliation |
NEC (NEC) |
7th Author's Name |
Shoji Ikeda |
7th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
8th Author's Name |
Takahiro Hanyu |
8th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
9th Author's Name |
Hideo Ohno |
9th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-04-11 14:20:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2013-6 |
Volume (vol) |
vol.113 |
Number (no) |
no.1 |
Page |
pp.27-32 |
#Pages |
6 |
Date of Issue |
2013-04-04 (ICD) |
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