Paper Abstract and Keywords |
Presentation |
2013-03-06 10:55
Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) VLD2012-155 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In order to perform more efficient Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, it is necessary to use complex sleep signal control. To achieve that, use of complex sleep control circuits is required. Complexity of circuits increases, a problem becomes more serious that the power consumption in complex sleep control circuit exceeds the reduced leakage power. We have investigated and evaluated several techniques to reduce power consumption by designing sleep signal circuits. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Fine Grain Power Gating / Low Power / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 451, VLD2012-155, pp. 105-110, March 2013. |
Paper # |
VLD2012-155 |
Date of Issue |
2013-02-25 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2012-155 |
Conference Information |
Committee |
VLD |
Conference Date |
2013-03-04 - 2013-03-06 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2013-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating |
Sub Title (in English) |
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Fine Grain Power Gating |
Keyword(2) |
Low Power |
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1st Author's Name |
Yoshihiro Tsurui |
1st Author's Affiliation |
Shibaura Institute of Technology (Shibaura Inst. of Tech.) |
2nd Author's Name |
Kimiyoshi Usami |
2nd Author's Affiliation |
Shibaura Institute of Technology (Shibaura Inst. of Tech.) |
3rd Author's Name |
Tatsunori Hashida |
3rd Author's Affiliation |
Shibaura Institute of Technology (Shibaura Inst. of Tech.) |
4th Author's Name |
Tetsuya Muto |
4th Author's Affiliation |
Shibaura Institute of Technology (Shibaura Inst. of Tech.) |
5th Author's Name |
Yuki Shimada |
5th Author's Affiliation |
Shibaura Institute of Technology (Shibaura Inst. of Tech.) |
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Speaker |
Author-1 |
Date Time |
2013-03-06 10:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2012-155 |
Volume (vol) |
vol.112 |
Number (no) |
no.451 |
Page |
pp.105-110 |
#Pages |
6 |
Date of Issue |
2013-02-25 (VLD) |
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