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Paper Abstract and Keywords
Presentation 2013-02-13 13:30
Characteristic Analysis of Signal Delay for Resistive Open Fault Detection
Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84
Abstract (in Japanese) (See Japanese page) 
(in English) When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistive open fault is difficult to test since some test patterns does not cause logical errors at the faulty circuit even if the pattern provides a transition at the faulty wire. In this study, we investigate the output characteristic of wires with a open fault using electromagnetic simulator for detecting resistive open faults. We apply simulation for several layouts to estimate the delay caused by the defect size, the length of adjacent lines, and different combinations of input signals at the adjacent lines. The simulated results show the effects of these parameters on the signal delay.
Keyword (in Japanese) (See Japanese page) 
(in English) resistive open fault / adjacent line / signal delay / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 429, DC2012-84, pp. 25-30, Feb. 2013.
Paper # DC2012-84 
Date of Issue 2013-02-06 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2013-02-13 - 2013-02-13 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2013-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Characteristic Analysis of Signal Delay for Resistive Open Fault Detection 
Sub Title (in English)  
Keyword(1) resistive open fault  
Keyword(2) adjacent line  
Keyword(3) signal delay  
1st Author's Name Hiroto Ohguri  
1st Author's Affiliation The University of Tokushima (Univ. of Tokushima)
2nd Author's Name Hiroyuki Yotsuyanagi  
2nd Author's Affiliation The University of Tokushima (Univ. of Tokushima)
3rd Author's Name Masaki Hashizume  
3rd Author's Affiliation The University of Tokushima (Univ. of Tokushima)
4th Author's Name Toshiyuki Tsutsumi  
4th Author's Affiliation Meiji University (Meiji Univ.)
5th Author's Name Koji Yamazaki  
5th Author's Affiliation Meiji University (Meiji Univ.)
6th Author's Name Yoshinobu Higami  
6th Author's Affiliation Ehime University (Ehime Univ.)
7th Author's Name Hiroshi Takahashi  
7th Author's Affiliation Ehime University (Ehime Univ.)
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Date Time 2013-02-13 13:30:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-DC2012-84 
Volume (vol) IEICE-112 
Number (no) no.429 
Page pp.25-30 
#Pages IEICE-6 
Date of Issue IEICE-DC-2013-02-06 

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