Paper Abstract and Keywords |
Presentation |
2013-02-13 13:30
Characteristic Analysis of Signal Delay for Resistive Open Fault Detection Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistive open fault is difficult to test since some test patterns does not cause logical errors at the faulty circuit even if the pattern provides a transition at the faulty wire. In this study, we investigate the output characteristic of wires with a open fault using electromagnetic simulator for detecting resistive open faults. We apply simulation for several layouts to estimate the delay caused by the defect size, the length of adjacent lines, and different combinations of input signals at the adjacent lines. The simulated results show the effects of these parameters on the signal delay. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
resistive open fault / adjacent line / signal delay / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 429, DC2012-84, pp. 25-30, Feb. 2013. |
Paper # |
DC2012-84 |
Date of Issue |
2013-02-06 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
DC2012-84 |
|