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Paper Abstract and Keywords
Presentation 2013-01-17 15:15
Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) VLD2012-134 CPSY2012-83 RECONF2012-88
Abstract (in Japanese) (See Japanese page) 
(in English) We develop an effective stencil computation accelerator by using multiple FPGAs, which employs 2D-mesh architecture connecting multiple small FPGAs. On the process of the development, there is a trouble that the system generates an illegal computation result when the multiple FPGA nodes are used. The cause of it is clock period variation. This paper describes a quantitative evaluation result of clock variations for every FPGA node and the design and implementation of a mechanism to operate the system successfully.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Stencil Computation / Clock-Domain / Synchronization Mechanism / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 377, RECONF2012-88, pp. 159-164, Jan. 2013.
Paper # RECONF2012-88 
Date of Issue 2013-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-134 CPSY2012-83 RECONF2012-88

Conference Information
Committee CPSY VLD RECONF IPSJ-SLDM  
Conference Date 2013-01-16 - 2013-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2013-01-CPSY-VLD-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Stencil Computation  
Keyword(3) Clock-Domain  
Keyword(4) Synchronization Mechanism  
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1st Author's Name Ryohei Kobayashi  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Shinya Takamaeda-Yamazaki  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Kenji Kise  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker
Date Time 2013-01-17 15:15:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-VLD2012-134,IEICE-CPSY2012-83,IEICE-RECONF2012-88 
Volume (vol) IEICE-112 
Number (no) no.375(VLD), no.376(CPSY), no.377(RECONF) 
Page pp.159-164 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2013-01-09,IEICE-CPSY-2013-01-09,IEICE-RECONF-2013-01-09 


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