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| Presentation | 2013-01-17 11:25 Low latency network topology using multiple links at each host Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII)  VLD2012-128 CPSY2012-77 RECONF2012-82 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | End-to-end network latency has become an important issue for parallel application on large-scale High Performance Computing (HPC) systems. It is thus necessary to build HPC systems as high-degree topologies by using high-radix switches. We have recently proposed a method to build topologies with such switches by adding random switch-to-switch links on a base regular topology. In this report, we extend the method by adding multiple links between a single host and multiple switches. Results obtained with flit-level discrete event simulation show that our random host-link topologies achieved comparable throughput with latency up to 51% lower than that of baseline topologies with link aggregation. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Topology / interconnection networks / high performance computing / high-radix switches / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 376, CPSY2012-77, pp. 123-128, Jan. 2013. | |
| Paper # | CPSY2012-77 | |
| Date of Issue | 2013-01-09 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-128 CPSY2012-77 RECONF2012-82 |
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| Conference Information | |
| Committee | CPSY VLD RECONF IPSJ-SLDM |
| Conference Date | 2013-01-16 - 2013-01-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2013-01-CPSY-VLD-RECONF-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low latency network topology using multiple links at each host |
| Sub Title (in English) | |
| Keyword(1) | Topology |
| Keyword(2) | interconnection networks |
| Keyword(3) | high performance computing |
| Keyword(4) | high-radix switches |
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| 1st Author's Name | Ryuta Kawano |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Ikki Fujiwara |
| 2nd Author's Affiliation | National Institute of Informatics (NII) |
| 3rd Author's Name | Hiroki Matsutani |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
| 5th Author's Name | Michihiro Koibuchi |
| 5th Author's Affiliation | National Institute of Informatics (NII) |
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| Speaker | Author-1 |
| Date Time | 2013-01-17 11:25:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | VLD2012-128, CPSY2012-77, RECONF2012-82 |
| Volume (vol) | vol.112 |
| Number (no) | no.375(VLD), no.376(CPSY), no.377(RECONF) |
| Page | pp.123-128 |
| #Pages | 6 |
| Date of Issue | 2013-01-09 (VLD, CPSY, RECONF) |
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