Paper Abstract and Keywords |
Presentation |
2013-01-17 14:25
Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-132 CPSY2012-81 RECONF2012-86 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we describe an implementation of a pupil detection using MaxCompiler which is a high-level synthesis framework for FPGA accelerators, and show comparison results with Verilog HDL design in terms of performance and an amount of user description. The MaxCompiler intends to accelerate high-performance computing application using deep-pipelined stream-oriented architectures which are generated by a Java-based language. As a result, our design achieved comparable performance with a design described by Verilog HDL while the required amount of the user description was about one-third. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-level synthesis / MaxCompiler / FPGA / Pupil detection / Computer Vision / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 377, RECONF2012-86, pp. 147-152, Jan. 2013. |
Paper # |
RECONF2012-86 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2012-132 CPSY2012-81 RECONF2012-86 |
Conference Information |
Committee |
CPSY VLD RECONF IPSJ-SLDM |
Conference Date |
2013-01-16 - 2013-01-17 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
RECONF |
Conference Code |
2013-01-CPSY-VLD-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool |
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Keyword(1) |
High-level synthesis |
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MaxCompiler |
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FPGA |
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Pupil detection |
Keyword(5) |
Computer Vision |
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1st Author's Name |
Keisuke Dohi |
1st Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
2nd Author's Name |
Yuichiro Shibata |
2nd Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
3rd Author's Name |
Kiyoshi Oguri |
3rd Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-01-17 14:25:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2012-132, CPSY2012-81, RECONF2012-86 |
Volume (vol) |
vol.112 |
Number (no) |
no.375(VLD), no.376(CPSY), no.377(RECONF) |
Page |
pp.147-152 |
#Pages |
6 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
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