Paper Abstract and Keywords |
Presentation |
2013-01-16 16:25
Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) VLD2012-119 CPSY2012-68 RECONF2012-73 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This article presents an improvement over the hardware accelerator
tightly coupled with a CPU. While the previously proposed method
assumes only a single fragment from a binary code to be synthesized
into an accelerator, our method attempts to accelerate multiple
fragments. Instead of connecting multiple acceleratos corresponding
to the fragments in parallel, a single hardware module is synthesized
which is capable of accelerating the multiple sections. This enables
sharing of datapath resources as well as the control among multiple
tasks, which makes the accelerator cost-efficient. Furthermore, the
capability of handling multiple code fragments makes it possible to
synthesize complex control structures, such as calling software
subroutines from a hardware accelerator, into hardware. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
embedded systems / hardware/software codesign / hardware accelerator / high-level synthesis / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 375, VLD2012-119, pp. 69-73, Jan. 2013. |
Paper # |
VLD2012-119 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2012-119 CPSY2012-68 RECONF2012-73 |
Conference Information |
Committee |
CPSY VLD RECONF IPSJ-SLDM |
Conference Date |
2013-01-16 - 2013-01-17 |
Place (in Japanese) |
(See Japanese page) |
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Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2013-01-CPSY-VLD-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu |
Sub Title (in English) |
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Keyword(1) |
embedded systems |
Keyword(2) |
hardware/software codesign |
Keyword(3) |
hardware accelerator |
Keyword(4) |
high-level synthesis |
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1st Author's Name |
Shunsuke Satake |
1st Author's Affiliation |
Kwansei Gakuin Universityu (Kwansei Gakuin Univ) |
2nd Author's Name |
Nagisa Ishiura |
2nd Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
3rd Author's Name |
Shimpei Tamura |
3rd Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
4th Author's Name |
Hiroyuki Tomiyama |
4th Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ) |
5th Author's Name |
Hiroyuki Kanbara |
5th Author's Affiliation |
Advanced Scientific Technology & Management Research Institute of KYOTO (ASTEM) |
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Speaker |
Author-1 |
Date Time |
2013-01-16 16:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2012-119, CPSY2012-68, RECONF2012-73 |
Volume (vol) |
vol.112 |
Number (no) |
no.375(VLD), no.376(CPSY), no.377(RECONF) |
Page |
pp.69-73 |
#Pages |
5 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
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