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Paper Abstract and Keywords
Presentation 2013-01-16 14:35
Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2012-115 CPSY2012-64 RECONF2012-69
Abstract (in Japanese) (See Japanese page) 
(in English) RSA encryption processing spends a lot of time on modular exponentiation of long word length, therefore the speed of the encryption is an important problem.
By introducing a signed-digit (SD) number arithmetic, residue arithmetic without carry propagation can be performed.
In this paper, we propose modulo $m$ multiplication circuits using signed-digit number arithmetic.
By performance evaluation of RSA encryption circuit using the proposed multiplication circuits, the RSA encryption processor has high performance in comparison with encryption processor based on binary arithmetic.
Keyword (in Japanese) (See Japanese page) 
(in English) Signed-Digit(SD) number / residue number system / SD modulo addition / SD modulo multiplication / RSA encryption / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 375, VLD2012-115, pp. 45-50, Jan. 2013.
Paper # VLD2012-115 
Date of Issue 2013-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-115 CPSY2012-64 RECONF2012-69

Conference Information
Committee CPSY VLD RECONF IPSJ-SLDM  
Conference Date 2013-01-16 - 2013-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2013-01-CPSY-VLD-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic 
Sub Title (in English)  
Keyword(1) Signed-Digit(SD) number  
Keyword(2) residue number system  
Keyword(3) SD modulo addition  
Keyword(4) SD modulo multiplication  
Keyword(5) RSA encryption  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Junichi Asaoka  
1st Author's Affiliation Gunma University (Gunma Univ.)
2nd Author's Name Yuuki Tanaka  
2nd Author's Affiliation Gunma University (Gunma Univ.)
3rd Author's Name Shugang Wei  
3rd Author's Affiliation Gunma University (Gunma Univ.)
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Speaker Author-1 
Date Time 2013-01-16 14:35:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-115, CPSY2012-64, RECONF2012-69 
Volume (vol) vol.112 
Number (no) no.375(VLD), no.376(CPSY), no.377(RECONF) 
Page pp.45-50 
#Pages
Date of Issue 2013-01-09 (VLD, CPSY, RECONF) 


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