IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2012-11-28 13:50
Control of Fine-Grain Power Gating by Detecting of the Virtual Ground Voltage
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)   エレソ技報アーカイブはこちら
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes fine-grain control to power gate function units using the charge up phenomenon of the virtual ground voltage by the leak current. This scheme reduces leakage power more effectively, because changing delay time by quantity of leak current. It has reduced the energy by 83% on average.
Keyword (in Japanese) (See Japanese page) 
(in English) Fine Grain Power Gating / Leak Monitor / Low Power / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 320, VLD2012-98, pp. 225-230, Nov. 2012.
Paper # VLD2012-98 
Date of Issue 2012-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Conference Date 2012-11-26 - 2012-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Centennial Hall Kyushu University School of Medicine 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2012 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Control of Fine-Grain Power Gating by Detecting of the Virtual Ground Voltage 
Sub Title (in English)  
Keyword(1) Fine Grain Power Gating  
Keyword(2) Leak Monitor  
Keyword(3) Low Power  
1st Author's Name Masaru Kudo  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech.)
2nd Author's Name Kimiyoshi Usami  
2nd Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2012-11-28 13:50:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2012-98,IEICE-DC2012-64 
Volume (vol) IEICE-112 
Number (no) no.320(VLD), no.321(DC) 
Page pp.225-230 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2012-11-19,IEICE-DC-2012-11-19 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan