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| Presentation | 2012-11-28 09:25 Routability-oriented Common-Centroid Capacitor Array Generation Jing Li, Bo Yang (Design Algorithm Lab.), Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)  VLD2012-89 DC2012-55 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We address layout generation of on-chip matched capacitors with the high relative accuracy. Unit capacitors are placed in a common-centroid capacitor array to reduce systematic mismatch induced by process gradient, while the post-placement routability is also being considered. This strategy is helpful for automatic layout generation of on-chip matched capacitors, and actually we had already applied it to the layout design of a SAR-ADC circuit. It is remarkable that compared with the common spiral capacitor array, our generation method (1) produces a similar low capacitance ration mismatch, and moreover (2) a $100\%$ routability could be achieved. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | analog layout design / common-centroid layout / capacitor array / systematic mismatch / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 320, VLD2012-89, pp. 171-175, Nov. 2012. | |
| Paper # | VLD2012-89 | |
| Date of Issue | 2012-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-89 DC2012-55 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2012-11-26 - 2012-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Centennial Hall Kyushu University School of Medicine |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2012 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Routability-oriented Common-Centroid Capacitor Array Generation |
| Sub Title (in English) | |
| Keyword(1) | analog layout design |
| Keyword(2) | common-centroid layout |
| Keyword(3) | capacitor array |
| Keyword(4) | systematic mismatch |
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| 1st Author's Name | Jing Li |
| 1st Author's Affiliation | Design Algorithm Labratory Inc. (Design Algorithm Lab.) |
| 2nd Author's Name | Bo Yang |
| 2nd Author's Affiliation | Design Algorithm Labratory Inc. (Design Algorithm Lab.) |
| 3rd Author's Name | Qing Dong |
| 3rd Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 4th Author's Name | Shigetoshi Nakatake |
| 4th Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
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| Speaker | Author-3 |
| Date Time | 2012-11-28 09:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2012-89, DC2012-55 |
| Volume (vol) | vol.112 |
| Number (no) | no.320(VLD), no.321(DC) |
| Page | pp.171-175 |
| #Pages | 5 |
| Date of Issue | 2012-11-19 (VLD, DC) |
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